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| CS1810xx, CS4961xx, & CM-2 Digital Audio Networking Processor CobraNet Silicon Series Version 2.3 TM CS18100x, CS18101x, CS18102x, and CM-2 CS49610x, CS49611x, and CS49612x Hardware User's Manual Preliminary Product Information http://www.cirrus.com This document contains information for a new product. Cirrus Logic reserves the right to modify this product without notice. (c)Copyright 2005 Cirrus Logic, Inc. JUN '05 DS651UM23 CobraNet Hardware User's Manual Table of Contents Table of Contents List of Figures......................................................................................................................................... 4 1.0 .Introduction ..................................................................................................................................... 5 2.0 Features ........................................................................................................................................... 6 2.1 CobraNet............................................................................................................................. 6 2.2 CobraNet Interface.............................................................................................................. 6 2.3 Host Interface...................................................................................................................... 7 2.4 Asynchronous Serial Interface ............................................................................................ 7 2.5 Synchronous Serial Audio Interface.................................................................................... 7 2.6 Audio Clock Interface .......................................................................................................... 7 2.7 Audio Routing and Processing............................................................................................ 7 3.0 Hardware.......................................................................................................................................... 8 4.0 Pinout and Signal Descriptions ........................................................................................................ 9 4.1 CS1810xx & CS4961xx Package Pinouts......................................................................... 10 4.1.1 CS1810xx/CS4961xx Pinout............................................................................. 10 4.1.2 CM-2 Connector Pinout..................................................................................... 11 4.2 Signal Descriptions ...........................................................................................................12 4.2.1 Host Port Signals ..............................................................................................12 4.2.2 Asynchronous Serial Port (UART Bridge) Signals ............................................ 12 4.2.3 Synchronous Serial (Audio) Signals.................................................................. 13 4.2.4 Audio Clock Signals .......................................................................................... 13 4.2.5 Miscellaneous Signals....................................................................................... 14 4.2.6 Power and Ground Signals ............................................................................... 14 4.2.7 System Signals ................................................................................................. 15 4.3 Characteristics and Specifications .................................................................................... 16 4.3.1 Absolute Maximum Ratings .............................................................................. 16 4.3.2 Recommended Operating Conditions ............................................................... 16 4.3.3 Digital DC Characteristics ................................................................................. 16 4.3.4 Power Supply Characteristics ........................................................................... 16 5.0 Synchronization.............................................................................................................................. 17 5.1 Synchronization Modes..................................................................................................... 17 5.1.1 Internal Mode .................................................................................................... 18 5.1.2 External Word Clock Mode ............................................................................... 18 5.1.3 External Master Clock Mode ............................................................................. 18 6.0 Digital Audio Interface .................................................................................................................... 19 6.1 Digital Audio Interface Timing ........................................................................................... 20 6.1.1 Normal Mode Data Timing ................................................................................ 21 6.1.2 I2S Mode Data Timing....................................................................................... 21 6.1.3 Standard Mode Data Timing ............................................................................. 22 7.0 Host Management Interface (HMI)................................................................................................. 23 7.1 Hardware........................................................................................................................... 23 7.4 Protocol and Messages..................................................................................................... 28 7.4.1 Messages.......................................................................................................... 28 7.4.1.1. Translate Address ................................................................................. 29 7.4.1.2. Interrupt Acknowledge........................................................................... 29 7.4.1.3. Goto Packet........................................................................................... 29 7.4.1.4. Goto Translation .................................................................................... 29 7.4.1.5. Packet Received ................................................................................... 30 7.4.1.6. Packet Transmit .................................................................................... 30 7.4.1.7. Goto Counters ....................................................................................... 30 7.4.2 Status ................................................................................................................ 31 2 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Table of Contents 7.4.3 Data................................................................................................................... 32 7.4.3.1. Region length ........................................................................................ 32 7.4.3.2. Writable Region ..................................................................................... 32 7.4.3.3. Translation Complete ............................................................................ 32 7.4.3.4. Packet Transmission Complete............................................................. 32 7.4.3.5. Received Packet Available .................................................................... 32 7.4.3.6. Message Togglebit ................................................................................ 32 8.0 HMI Reference Code ..................................................................................................................... 33 8.1 HMI Definitions.................................................................................................................. 33 8.2 HMI Access Code ............................................................................................................. 34 8.3 CM-1, CM-2 Auto-detection ..............................................................................................36 9.0 Mechanical Drawings and Schematics .......................................................................................... 37 9.1 CM-2 Mechanical Drawings ..............................................................................................38 9.2 CM-2 Schematics.............................................................................................................. 44 9.3 CS1810xx/CS4961xx Package ......................................................................................... 51 9.4 Temperature Specifications ..............................................................................................52 10.0 Ordering Information .................................................................................................................... 53 10.1 Device Part Numbers ...................................................................................................... 53 10.2 Device Part Numbering Scheme..................................................................................... 53 DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 3 CobraNet Hardware User's Manual List of Figures List of Figures Figure 1. CobraNet Data Services ......................................................................................................... 5 Figure 2. CobraNet Interface Hardware Block Diagram......................................................................... 8 Figure 3. Audio Clock Sub-system....................................................................................................... 17 Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) CS18100x/CS49610x & CS18101x/CS49611x ............................................................ 19 Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) CS18102x/CS49612x ................................................................................................... 19 Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1..................................... 20 Figure 7. Serial Port Data Timing Overview......................................................................................... 20 Figure 8. Audio Data Timing Detail - Normal Mode, 64FS CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 21 Figure 9. Audio Data Timing Detail - Normal Mode, 128FS CS18102x/CS49612x ................................................................................................... 21 Figure 10. Audio Data Timing Detail - I2S Mode, 64FS CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 21 Figure 11. Audio Data Timing Detail - I2S Mode, 128FS CS18102x & CS49612x................................................................................................ 21 Figure 12. Audio Data Timing Detail - Standard Mode, 64FS CS18100x/CS49610x, CS18101x/CS49611x .............................................................. 22 Figure 13. Audio Data Timing Detail - Standard Mode, 128FS CS18102x/CS49612x ................................................................................................... 22 Figure 14. Host Port Read Cycle Timing - Motorola Mode .................................................................. 25 Figure 15. Host Port Write Cycle Timing - Motorola Mode................................................................... 25 Figure 16. Parallal Control Port - Intel Mode Read Cycle .................................................................... 27 Figure 17. Parallel Control Port - Intel Mode Write Cycle .................................................................... 27 Figure 18. CM-2 Module Assembly Drawing, Top ............................................................................... 38 Figure 19. CM-2 Module Assembly Drawing, Bottom .......................................................................... 39 Figure 20. General PCB Dimensions ................................................................................................... 40 Figure 21. Example Configuration, Side View...................................................................................... 41 Figure 22. Faceplate Dimensions ........................................................................................................ 42 Figure 23. Connector Detail ................................................................................................................. 43 Figure 24. CM-2 RevF Schematic Page 1 of 7 .................................................................................... 44 Figure 25. CM-2 RevF Schematic Page 2 of 7 .................................................................................... 45 Figure 26. CM-2 RevF Schematic Page 3 of 7 .................................................................................... 46 Figure 27. CM-2 RevF Schematic Page 4 of 7 .................................................................................... 47 Figure 28. CM-2 RevF Schematic Page 5 of 7 .................................................................................... 48 Figure 29. CM-2 RevF Schematic Page 6 of 7 .................................................................................... 49 Figure 30. CM-2 RevF Schematic Page 7 of 7 .................................................................................... 50 Figure 31. 144-Pin LQFP Package Drawing ........................................................................................ 51 Figure 32. Device Part Numbering Explanation ................................................................................... 53 4 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Introduction 1.0 Introduction This document is intended to help hardware designers integrate the CobraNetTM interface into an audio system design. It covers the CS18100x, CS18101x, CS18102x, CS49610x, CS49611x, and CS49612x members of the CobraNetTM Silicon Series of devices, where "x" is the ROM version (ROM ID). This document also describes the CM-2 module with schematics, mechanical drawings, etc. CobraNet is a combination of hardware (the CobraNet interface), network protocol, and firmware. CobraNet operates on a switched Ethernet network and provides the following additional communications services. * Isochronous (Audio) Data Transport * Sample Clock Distribution * Control and Monitoring Data Transport The CobraNet interface performs synchronous-to-isochronous and isochronous-tosynchronous conversions as well as the data formatting required for transporting real-time digital audio over the network. The CobraNet interface has provisions for carrying and utilizing control and monitoring data such as Simple Network Management Protocol (SNMP) through the same network connection as the audio. Standard data transport capabilities of Ethernet are shown here as unregulated traffic. Since CobraNet is Ethernet based, in most cases, data communications and CobraNet applications can coexist on the same physical network. Figure 1 illustrates the different data services available through the CobraNet system. Isochronous Data Isochronous Data (Audio) (Audio) Ethernet Ethernet Unregulated Unregulated Traffic Traffic Control Data Control Data Clock Figure 1. CobraNet Data Services DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 5 CobraNet Hardware User's Manual Features 2.0 Features 2.1 CobraNet * Real-time Digital Audio Distribution via Ethernet * No Overall Limit on Network Channel Capacity * Fully IEEE 802.3 Ethernet Standards Compliant * Fiber optic and gigabit Ethernet variants are fully supported. * Ethernet infrastructure can be used simultaneously for audio and data communications. * Free CobraCADTM Audio Network Design Tool * High-quality Audio Sample Clock Delivery Over Ethernet * Bit-transparent 16-, 20-, and 24-bit Audio Transport * Professional 48-kHz and 96-kHz sample rate * Select Latency as Low as 1.33ms * Flexible Many-to-many Network Audio Routing Capabilities * Reduced-cost, Improved-performance, Convergent Audio Distribution Infrastructure 2.2 CobraNet Interface * 120 MIPS Customer-configurable Audio DSP * Auto-negotiating 100Mbit Full-duplex Ethernet Connections * Up to 32-channel Audio I/O Capability * Implements CobraNet Protocol for real-time transport of audio over Ethernet. * Local Management via 8-bit Parallel Host Port * UDP/IP Network Stack with Dynamic IP Address Assignment via BOOTP or RARP * Remote Management via Simple Network Management Protocol (SNMP) * Economical Three-chip Solution * Available Module form factor allows for flexible integration into audio products. * Non-volatile Storage of Configuration Parameters * Safely Upgrade Firmware Over Ethernet Connection * LED Indicators for Ethernet Link, Activity, Port Selection, and Conductor Status * Watchdog Timer Output for System Integrity Assurance * Comprehensive Power-on Self-test (POST) * Error and Fault Reporting and Logging Mechanisms 6 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Features 2.3 Host Interface * 8-bit Data, 4-bit Address * Virtual 24-bit Addressing with 32-bit Data * Polled, Interrupt, and DMA Modes of Operation * Configure and Monitor CobraNet Interface * Transmit or Receive Ethernet Packets at Near-100-Mbit Wire Speed 2.4 Asynchronous Serial Interface * Full-duplex Capable * 8-bit Data Format * Supports all Standard Baud Rates 2.5 Synchronous Serial Audio Interface * Up to Four Bi-directional Interfaces Supporting up to 32 Channels of Audio I/O * 64FS (3.072 MHz) Bit Rate for CS18100x/CS49610x and CS18101x/ CS49611x * 128FS (6.144 MHz) Bit Rate for CS18102x/CS49612x * Accommodates Many Synchronous Serial Formats Including I2S * 32-bit Data Resolution on All Audio I/O 2.6 Audio Clock Interface * 5 Host Audio-clocking Modes for Maximum Flexibility in Digital Audio Interface Design * Low-jitter Master Audio Clock Oscillator (24.576 MHz) * Synchronize to Supplied Master and/or Sample Clock * Sophisticated jitter attenuation assures network perturbations do not affect audio performance. 2.7 Audio Routing and Processing * Single-channel Granularity in Routing From Synchronous Serial Audio Interface to CobraNet Network * Two levels of inward audio routing affords flexibility in audio I/O interface design in the host system. * Local Audio Loopback and Output Duplication Capability * Peak-read Audio Metering with Ballistics DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 7 CobraNet Hardware User's Manual Hardware 3.0 Hardware Figure 2 shows a high-level view of the CobraNet CM-2 interface hardware architecture. Clock VCXO Control Clock Flash Memory CobraNet CM-2 Module Audio Serial Host CS1810xx/ CS4961xx Ethernet Controller Ethernet Magnetics Figure 2. CobraNet Interface Hardware Block Diagram Flash memory holds the CobraNet firmware and management interface variable settings. The CS1810xx or CS4961xx network processor is the heart of the CobraNet interface. It implements the network protocol stacks and performs the synchronous-to-isochronous and isochronous-to-synchronous conversions. The network processor has a role in sample clock regeneration and performs all interactions with the host system. The sample clock is generated by a voltage-controlled crystal oscillator (VCXO) controlled by the network processor. The VCXO frequency is carefully adjusted to achieve lock with the network clock. The Ethernet controller is a standard interface chip that implements the 100-Mbit Fast Ethernet standard. As per Ethernet requirements the interface is transformer isolated. 8 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Pinout and Signal Descriptions 4.0 Pinout and Signal Descriptions This section details the chip pinout and signal interfaces for each module and is divided as follows: * "CS1810xx & CS4961xx Package Pinouts" on page 10 * "Host Port Signals" on page 12 * "Asynchronous Serial Port (UART Bridge) Signals" on page 12 * "Synchronous Serial (Audio) Signals" on page 13 * "Audio Clock Signals" on page 13 * "Miscellaneous Signals" on page 14 * "Power and Ground Signals" on page 14 * "System Signals" on page 15 DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 9 CobraNet Hardware User's Manual Pinout and Signal Descriptions 4.1 CS1810xx & CS4961xx Package Pinouts 4.1.1 CS1810xx/CS4961xx Pinout Table 1 lists the pinout for the 144-pin LQFP CS1810xx/CS4961xx device. The interfaces for these signals are expanded in the following sections. Table 1. CS1810xx/CS4961xx Pin Assignments Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Pin Name VCXO_CTRL MCLK_SEL DBDA DBCK NC NC NC DAO_MCLK TEST VDDD HS3 NC GND DAO2_LRCLK DAO1_DATA3 DAO1_DATA2/HS2 DAO1_DATA1/HS1 VDDIO DAO1_DATA0/HS0 DAO1_SCLK GND DAO1_LRCLK UART_TX_OE VDDD UART_TXD UART_RXD GND NC DATA7 DATA6 DATA5 DATA4 VDDIO DATA3 DATA2 GND Pin # 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 WE Pin Name DATA1 Pin # 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 Pin Name VDDIO ADDR10 ADDR14 GND ADDR13 NC NC NC NC ADDR15 VDDD ADDR16 ADDR17 GND ADDR18 ADDR19 OE CS1 VDDIO MUTE HRESET GND WATCHDOG IOWAIT REFCLK_IN VDDD GPIO0 GPIO1 GND HACK HDS HEN HADDR3 HADDR2 HR/W GPIO2 Pin # 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 Pin Name HADDR1 HADDR0 HDATA7 HDATA6 VDDIO HDATA5 HDATA4 GND HDATA3 HDATA2 VDDD HDATA1 HDATA0 GND XTAL_OUT XTO XTI GND_a FILT2 FILT1 VDDA VDDD DAI1_DATA3 DAI1_DATA2 GND DAI1_DATA1 DAI1_DATA0 VDDIO DAI1_SCLK DAI1_LRCLK GND HREQ NC NC IRQ1 IRQ2 DATA0 DATA15 DATA14 DATA13 DATA12 VDDIO DATA11 DATA10 GND DATA9 DATA8 NC NC NC NC VDDD ADDR12 ADDR11 GND ADDR9 ADDR8 VDDIO ADDR7 ADDR6 GND ADDR5 CS2 VDDD ADDR4 ADDR3 GND ADDR2 ADDR1 ADDR0 10 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Pinout and Signal Descriptions 4.1.2 CM-2 Connector Pinout Table 1 lists the pinout for the four pinout connectors on the CM-2 board (J1-J4). The interfaces for these signals are expanded following the table. Table 2. CM-2 Pin Assignments Conn. J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 Pin # A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 Pin Name UART_RXD UART_TX_OE HACK HR/W HDS HREQ HEN HADDR0 HADDR1 HADDR2 HDATA0 HDATA1 HDATA2 HDATA3 HDATA4 HDATA5 HDATA6 HRESET HDATA7 HADDR3 UART_TXD GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V Conn. J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J1/J2 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 Pin # B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 GND Pin Name VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V RSVD1 GND VCC_+3.3V RSVD2 MUTE FS1 MCLK_OUT MCLK_IN REFCLK_IN DAO1_SCLK/DAI1_SCLK DAO1_DATA0 DAO1_DATA1 DAO1_DATA2 DAO1_DATA3 DAI1_DATA0 DAI1_DATA1 DAI1_DATA2 Conn. J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 J3/J4 Pin # A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 Pin Name DAI1_DATA3 RSVD3 WATCHDOG RSVD4 AUX_POWER2 AUX_POWER0 GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V GND VCC_+3.3V GND GND VCC_+5V VCC_+5V AUX_POWER3 AUX_POWER1 DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 11 CobraNet Hardware User's Manual Pinout and Signal Descriptions 4.2 Signal Descriptions 4.2.1 Host Port Signals The host port is used to manage and monitor the CobraNet interface. Electrical operation and protocol is detailed in the "Host Management Interface (HMI)" on page 23 of this Manual. The host port can operate in two modes in order to accomodate Motorola(R) or Intel(R) style interfaces. The default mode is Motorola. Intel mode is set via a firmware modification. Table 2-1: Host Port Signals Signal Description Direction CM-2 Pin # J1:A19, A[17:11] J1:A20, A[10:8] J1:A4 J1:A4 J1:A6 J1:A3 J1:A5 J1:A5 J1:A7 J1:A7 CS1810xx/ CS4961xx Pin # 111, 112, 114, 115, 117, 118, 102, 121 105, 106, 109,110 107 107 140 102 103 103 104 104 Host port data. Notes HDATA[7:0] Host Data In/Out HADDR[3:0] HRW HRD HREQ HACK HDS HWR HEN HCS Host Address Host Direction Host Read Host Request Host Alert Host Strobe Host Write Host Enable Select In In In Out Out In In In In Host port address. Host port transfer direction (Motorola mode). Host Read (Intel mode). Host port data request. Host port interrupt request. Host port strobe (Motorola mode). Host Write (Intel mode). Host Port Enable. Select (Intel mode). 4.2.2 Asynchronous Serial Port (UART Bridge) Signals Level-shifting drive circuits are typically required between these signals and any external connections. Signal UART_RXD UART_TXD UART_TX_OE Description Asynchronous Serial Receive Data Asynchronous Serial Transmit Data Transmit Drive Enable Direction In Out Out CM-2 Pin # J1:A1 J1:B1 J1:A2 CS1810xx/ CS4961xx Pin # 26 25 23 Notes Pull-up to VCC if unused. Enable transmit (active high) drive for two wire multi-drop interface. 12 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Pinout and Signal Descriptions 4.2.3 Synchronous Serial (Audio) Signals The synchronous serial interfaces are used to bring digital audio into and out of the system. Typically the synchronous serial is wired to ADCs and/or DACs. Detailed timing and format is described in "Digital Audio Interface" on page 19. CM-2 Pin # CS1810xx/ CS4961xx Pin # Signal Description Direction Notes Synchronous serial bit clock. 64 FS for CS18100x & CS49610x (2x1 channel) 64 FS for CS18101x & CS49611x (2x4 channels) 128 FS for CS18102x & CS49612x (4x4 channels) Typically tied to DAI1_SCLK. Output synchronous serial audio data DAO1_DATA[3:1] not used for CS18100x & CS49610x. DAO1_SCLK Audio Bit Clock Out J3:A7 20 DAO1_DATA[3:0] Audio Output Data Out J3:A18, B18 15-17, 19 DAI1_DATA[3:0] Audio Input Data In Input synchronous serial audio data J3: 131, 132, 134, 135 DAI1_DATA[3:1] not used for CS18100x & A[15:12] CS49610x. J4:A7 137 Should be tied to DAO1_SCLK. Synchronous serial bit clock. DAI1_SCLK Audio Bit Clock In 4.2.4 Audio Clock Signals See "Synchronization" on page 17 for an overview of synchronization modes and issues. CM-2 Pin # CS1810xx/ CS4961xx Pin # 138 J3:A3 J3:A3 22 14 Signal DAI1_LRCLK DAO1_LRCLK (FS1) DAO2_LRCLK (FS1) Description Sample clock input Sample clock output Sample clock output Direction In Out Out Notes Should be tied to DAO1_LRCLK for all devices. FS1 (word clock) for CS18100x/CS49610x and CS18101x/CS49611x. FS1 (word clock) for CS18102x & CS49612x. Clock input for synchronizing network to an external clock source, for redundancy control and synchronization of FS divider chain to external source. See "Synchronization" on page 17 for more detail. For systems featuring multiple CobraNet interfaces operating off a common master clock. See "Synchronization" on page 17 for more detail. Low jitter 24.576 MHz master audio clock. REFCLK_IN Reference clock In J3:A6 97 MCLK_IN Master audio clock input Master audio clock output In J3:A5 8* MCLK_OUT Out J3:A4 8* *An external multiplexor controlled by this pin is required for full MCLK_IN and MCLK out implementation. DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 13 CobraNet Hardware User's Manual Pinout and Signal Descriptions 4.2.5 Miscellaneous Signals Signal HRESET Description Reset Direction In CM-2 Pin # J1:A18 CS1810xx/ CS4961xx Pin # 93 Notes System reset (active low). 10 ns max rise time. 1 ms min assertion time. Toggles at 750 Hz nominal rate to indicate proper operation. Period duration in excess of 200 ms indicates hardware or software failure has occurred and the interface should be reset. Note that improper operation can also be indicated by short pulses (<100 ns). Asserts (active low) during initialization and when a fault is detected or connection to the network is lost. WATCHDOG Watch Dog Out J3:A17 95 MUTE NC Interface Ready No Connect Out - J3:A2 - 92 28, 50-53, 7881, 141, 142 4.2.6 Power and Ground Signals Signal Description CM-2 Pin # J1:B20, B17, B15, B13, B11, B9, B7, B5, B3 J3:B14, B12, B10, B8, B6, B4, B2 CS1810xx/CS4961xx Pin # Specification VCC_+3V System Digital +3.3 v N/A 3.3 0.3v, 500 mA Typ., 750 mA Max. VCC_+5V VDDD VDDIO VDDA AUX_POWER [3-0] J3;B[18:17] N/A N/A N/A J3:B[20:19], A[20:19] J1:B19, B16, B14, B12, B10, B8, B6, B4, B2 N/A 10, 24, 54, 66, 83, 98, 119, 130 18, 33, 44, 60, 73, 91, 113, 136 129 N/A Backwards Compatibility +1.8 V @ 500mA Typ. for Core Logic +3.3 V @ 120mA Typ. for I/O Logic Filtered +1.8 V @ 10mA Typ. GND Digital Ground J3:B16, B15, B13, B11, B9, B7, B5, B3, B1 13, 21, 27, 36, 47, 57, 63, 69, 76, 86, 94, 101, 116, 122, 126, 133, 139 14 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Pinout and Signal Descriptions 4.2.7 System Signals Use these CS1810xx/CS4961xx signals stricktly in the manner described in CM-2 Schematics (Section 9.2 on page 44). Each signal is briefly described below. Signal VCXO_CTRL MCLK_SEL DBDA, DBCK TEST DATA[15:0] Description A Delta-sigma DAC Output for Controlling the On-board VCXO Control Signal for Selecting MCLK Sources I2C Debugger Interface Used for testing during manufacturing. Keep grounded for normal operation. Data Bus for Flash & Ethernet Controller(s) CS1810xx/CS4961xx Pin # 1 2 3, 4 9 29-32, 34, 35, 37, 39-43, 45, 46, 48, 49 55, 56, 58, 59, 61, 62, 64, 67, 68, 70-72, 74, 75, 77, 82, 84, 85, 87, 88 38 90 65 89 96 99, 100, 108 125 124 123 127, 128 8 11, 16, 17, 19 ADDR[19:0] WE CS1 CS2 OE IOWAIT GPIO[2:0] XTI XTO XTAL_OUT FILT2, FILT1 DAO_MCLK HS[3:0] Address Bus for Flash & Ethernet Controller(s) Write Enable for Flash and Ethernet Controller(s) Chip Select for Flash Memory Device Chip Select for Ethernet Controller(s) Output Enable Wait State Signal from Ethernet Controller(s) General-purpose I/O Signals Reference Clock Input / Crystal Oscillator Input Crystal Oscillator Output A Buffered Version of XTI PLL Loop Filter MCLK Input CS1810xx/CS4961xx Boot Mode Selection DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 15 CobraNet Hardware User's Manual Pinout and Signal Descriptions 4.3 Characteristics and Specifications Parameter Symbol VDD VDDA VDDIO Iin Vfilt Vinio Tstg Min -0.3 -0.3 -0.3 -65 Max 2.0 2.0 5.0 0.3 +/- 10 2.0 5.0 150 Unit V V V V mA V V C 4.3.1 Absolute Maximum Ratings DC power supplies: Core supply PLL supply I/O supply |VDDA - VDD| Input current, any pin except supplies Input voltage on FILT1, FILT2 Input voltage on I/O pins Storage temperature Caution: Operation at or beyond these limits may result in permanent damage to the device. Normal operation is not guaranteed at these extremes. 4.3.2 Recommended Operating Conditions Parameter DC power supplies: Core supply PLL supply I/O supply |VDDA - VDD| - CQ - DQ Symbol VDD VDDA VDDIO TA 0 - 40 Min 1.71 1.71 3.13 Typ 1.8 1.8 3.3 + 70 + 85 Max 1.89 1.89 3.46 0.3 Unit V V V V C Ambient operating temperature 4.3.3 Digital DC Characteristics (measurements performed under static conditions.) Parameter High-level input voltage Low-level input voltage, except XTI Low-level input voltage, XTI Input Hysteresis High-level output voltage at IO = -8.0 mAO = -16.0 mA Low-level output voltage at IO = 8.0 mAO = -16.0 mA Input leakage current (all pins without internal pullup resistors except XTI) Input leakage current (pins with internal pull-up resistors, XTI) Symbol VIH VIL VILXTI Vhys VOH VOL IIN IIN-PU Min 2.0 VDDIO * 0.9 - Typ 0.3 - Max 0.8 0.6 VDDIO * 0.1 5 50 Unit V V V V V V A A 4.3.4 Power Supply Characteristics (measurements performed under operating conditions)) Parameter Power supply current: Core and I/O operating: VDD PLL operating: VDDA With external memory and most ports operating: VDDIO Min (Note 1) - Typ 500 10 120 Max - Unit mA mA mA NOTES:1. Dependent on application firmware and DSP clock speed. 16 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Synchronization 5.0 Synchronization Figure 3 shows clock related circuits for the CS1810xx/CS4961xx and board design (CM-2). This circuitry allows the synchronization modes documented below to be achieved. Modes are distinguished by different settings of the multiplexors and software elements. MCLK_OUT DAC VCXO 24.576 MHz AClkConfig CS1810xx/CS4961xx Audio Clock Generator Sample Phase Counter Phase Detector Edge Detect Loop Filter FS1 MCLK_IN SLCK MCLK_SEL RefClkEnable RefClkPolarity REFCLK_IN BeatReceived Legend: External Hardware Component (CM2) Internal Hardware Component (CS1810xx, CS4961xx) Software Component Figure 3. Audio Clock Sub-system 5.1 Synchronization Modes Clock synchronization mode for conductor and performer roles is independently selectable via management interface variables syncConductorClock and syncPerformerClock. The role (conductor or performer) is determined by the network environment including the conductor priority setting of the device and the other devices on the network. It is possible to ensure you will never assume the conductor role by selecting a conductor priority of zero. However, it is not reasonable to assume that by setting a high conductor priority, you will always assume the conductor role. For more information, refer to CobraNet Programmer's Reference Manual. DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 17 CobraNet Hardware User's Manual Synchronization The following synchronization modes are further described below: * "Internal Mode" on page 18 * "External Word Clock Mode" on page 18 * "External Master Clock Mode" on page 18 5.1.1 Internal Mode All CobraNet clocks are derived from the onboard VCXO. The master clock generated by the VCXO is available to external circuits via the master clock output. Conductor--The VCXO is "parked" according to the syncClockTrim setting. Performer--The VCXO is "steered" to match the clock transmitted by the Conductor. 5.1.2 External Word Clock Mode All CobraNet clocks are derived from the onboard VCXO. The VCXO is steered from an external clock supplied to the reference clock input. The clock supplied can be any integral division of the sample clock in the range of 750Hz to 48kHz. External synchronization lock range: 5 s. This specification indicates drift or wander between the supplied clock and the generated network clock at the conductor. Absolute phase difference between the supplied reference clock and generated sample clock is dependant on network topology. Conductor--This mode gives a means for synchronizing an entire CobraNet network to an external clock. Performer--The interface disregards the fine timing information delivered over the network from the conductor. Coarse timing information from the conductor is still used; fine timing information is instead supplied by the reference clock. The external clock source must be synchronous with the network conductor. This mode is useful in installations where a house sync source is readily available. 5.1.3 External Master Clock Mode The VCXO is disabled and MCLK_IN is used as the master clock for the node. This is a "hard" synchronization mode. The supplied clock is used directly by the CobraNet interface for all timing. This mode is primarily useful for devices with multiple CobraNet interfaces sharing a common master audio clock. The supplied clock must be 24.576 MHz. The supplied clock must have a 37 ppm precision. Conductor--The entire network is synchronized to the supplied master clock. Performer--The node will initially lock to the network clock and will "jam sync" via the supplied master clock. The external clock source must be synchronous with the network conductor. 18 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Digital Audio Interface 6.0 Digital Audio Interface The CS18101x/CS49611x, CS18102x/CS49612x, and CM-2 support four bi-directional synchronous serial interfaces. The CS18100x & CS49610x support one bi-directional synchronous serial interface. All interfaces operate in master mode with DAO1_SCLK as the bit clock and FS1 as the frame clock. A sample period worth of synchronous serial data includes two (or four) audio channels. CobraNet supports two synchronous serial bit rates: 48 Khz and 96 KHz. However, 96 kHz sample rate is not available when using CS18102x/CS49612x with 16X16 channels. Bit rate is selected by the modeRateControl variable. All synchronous serial interfaces operate from a common clock at the same bit rate. FS1 D A O 1 _ D A T A 0 / D A I1 _ D A T A 0 *D A O 1 _ D A T A 1 / D A I1 _ D A T A 1 *D A O 1 _ D A T A 2 / D A I1 _ D A T A 2 *D A O 1 _ D A T A 3 / D A I1 _ D A T A 3 * N o t p re s e n t in C S 1 8 1 0 0 x o r C S 4 9 6 1 0 x . Figure 4. Channel Structure for Synchronous Serial Audio at 64FS (One Sample Period) - CS18100x/CS49610x & CS18101x/CS49611x 1 3 5 7 2 4 6 8 FS1 DAO1_DATA0 / DAI1_DATA0 DAO1_DATA1 / DAI1_DATA1 DAO1_DATA2 / DAI1_DATA2 DAO1_DATA3 / DAI1_DATA3 1 5 9 13 2 6 10 14 3 7 11 15 4 8 12 16 Figure 5. Channel Structure for Synchronous Serial Audio at 128FS (One Sample Period) - CS18102x/CS49612x Default channel ordering is shown above. Note that the first channel always begins after the rising or falling edge of FS1 (depending on the mode). DAI1_SCLK period depends on the sample rate selected. Up to 32 significant bits are received and buffered by the DSP for synchronous inputs. Up to 32 significant bits are transmitted by the DSP for synchronous outputs. Bit 31 is always the most significant (sign) bit. A 16-bit audio source must drive to bit periods 31-16 with audio data and bits 15-0 should be actively driven with either a dither signal or zeros. Cirrus Logic recommends driving unused LS bits to zero. DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 19 CobraNet Hardware User's Manual Digital Audio Interface Although data is always transmitted and received with a 32-bit resolution by the synchronous serial ports, the resolution of the data transferred to/from the Ethernet may be less. Incoming audio data is truncated to the selected resolution. Unused least significant bits on outgoing data is zero filled. 6.1 Digital Audio Interface Timing 0 - 5ns MCLK_OUT DAO1_SCLK FS1 0 - 10ns Figure 6. Timing Relationship between FS512_OUT, DAO1_SCLK and FS1 An DAO1_SCLK edge follows an MCLK_OUT edge by 0.0 to 5.0ns. An FS1 edge follows a MCLK_OUT edge by 0.0 to 10.0ns. Note: The DAO1_SCLK and FS1 might be synchronized with the either the falling edge or the rising edge of MCLK_OUT. Which edge is impossible to predict since it depends on power up timing. 5ns DAO1_SCLK DAI1_DATAx DAO1_DATAx 0 - 12ns Figure 7. Serial Port Data Timing Overview 0ns Setup times for DAI1_DATAx and FS1 are 5.0 ns with a hold time of 0.0 ns with respect to the DAI1_SCLK edge. Clock to output times for DAO1_DATAx is 0.0 to 12.0 ns from the edge of DAO1_SCLK. 20 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Digital Audio Interface 6.1.1 Normal Mode Data Timing DAI1_SCLK FS1 DAI1_DATAx DAO1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 432 1 1 0 0 Unused Unused 23 23 8765432 Figure 8. Audio Data Timing Detail - Normal Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x DAI1_SCLK FS1 DAI1_DATAx DAO1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Unused 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Unused 23 23 Figure 9. Audio Data Timing Detail - Normal Mode, 128FS - CS18102x/CS49612x Each audio channel is comprised of 32 bits of data, regardless of audio sample size. The figure above shows 24-bit audio data. The MSB is left justified and is aligned with FS1. Data is sampled on the rising edge of DAI_SCLK and data changes on the falling edge. 6.1.2 I2S Mode Data Timing DAI1_SCLK FS1 DAI1_DATAx DAO1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 432 1 1 0 0 Unused Unused 23 23 8765432 Figure 10. Audio Data Timing Detail - I2S Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x DAI1_SCLK FS1 DAI1_DATAx DAO1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Unused 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Unused 23 23 Figure 11. Audio Data Timing Detail - I2S Mode, 128FS - CS18102x & CS49612x Each audio channel is comprised of 32 bits of data, regardless of audio sample size. The figure above shows 24-bit audio data. The MSB is left justified and arrives one bit period following FS1. Data is sampled on the rising edge of DAI_SCLK and data changes on the falling edge. DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 21 CobraNet Hardware User's Manual Digital Audio Interface 6.1.3 Standard Mode Data Timing DAI1_SCLK FS1 DAI1_DATAx DAO1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 765 432 32 1 1 0 0 Unused Unused 23 23 876 54 Figure 12. Audio Data Timing Detail - Standard Mode, 64FS - CS18100x/CS49610x, CS18101x/CS49611x DAI1_SCLK FS1 DAI1_DATAx DAO1_DATAx 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Unused 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Unused Unused 23 23 Figure 13. Audio Data Timing Detail - Standard Mode, 128FS - CS18102x/CS49612x Each audio channel is comprised of 32 bits of data, regardless of audio sample size. The figure above shows 24-bit audio data. The MSB is left justified and is aligned with FS1. Data is sampled on the rising edge of DAI_SCLK and data changes on the falling edge. 22 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Host Management Interface (HMI) 7.0 Host Management Interface (HMI) 7.1 Hardware The host port is 8 bits wide with 4 bits of addressing. Ten of the 16 addressable registers are implemented. The upper two registers can be used to configure and retrieve the status on the host port hardware. However, only the first 8 are essential for normal HMI communications. It is therefore feasible, in most applications, to utilize only the first 3 address bits and tie the most significant bit (A3) low. Host port hardware supports Intel(R) (little-endian), Motorola(R), and Motorola multiplexed bus (big-endian) protocols. Standard CobraNet firmware configures the port in the Motorola, big-endian mode. The host port memory map is shown in Table 3. Refer also to "HMI Definitions" on page 33 and "HMI Access Code" on page 34. Host Address 0 1 2 3 4 5 6 7 8 9 Message A (MS) Message B Message C Message D (LS) Data A (MS) Data B Data C Data D (LS) Control Status Register Table 3. Host port memory map The message and data registers provide separate bi-directional data conduits between the host processor and the CS1810xx/CS4961xx. A 32-bit word of data is transferred to the CS1810xx/CS4961xx when the host writes the D message or data register after presumably previously writing the A, B, and C registers with valid data. Data is transferred from the CS1810xx/CS4961xx following a read of the D message or data register. Again, presumably the A, B, and C registers are read previously. Two additional hardware signals are associated with the host port: HACK and HREQ. Both are outputs to the host. HACK may be wired to an interrupt request input on the host. HACK can be made to assert (logic 0) on specific events as specified by the hackEnable MI variable. HACK is deasserted (logic 1) by issuance of the Acknowledge Interrupt message (see "Messages" below). DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 23 CobraNet Hardware User's Manual Host Management Interface (HMI) HREQ may be wired to a host interrupt or DMA request input. HREQ is used to signal the host that data is available (read case, logic 0) or space is available in the host port data channel (write case, logic 1). The read and write case are distinguished by the HMI based on the preceding message. Identify, Goto Translation (read), Goto Packet (read) and Goto Counters cause HREQ to represent read status. Goto Translation (write) and Goto Packet (write) switch HREQ to write mode. All other commands have no effect on HREQ operation. In general, the host can read from the CS1810xx/CS4961xx when HREQ is low and can write data to CS1810xx/CS4961xx when HREQ is high. 7.2 Host Port Timing - Motorola(R) Mode (CL = 20 pF) Parameter Address setup before HEN and HDS low Address hold time after HEN and HDS low Read Delay between HDS then HEN low or HEN then HDS low Data valid after HEN and HDS low with HRW high HEN and HDS low for read Data hold time after HEN or HDS high after read Data high-Z after HEN or HDS high after read HEN or HDS high to HEN and HDS low for next read HEN or HDS high to HEN and HDS low for next write HR/W rising to HREQ falling Write Delay between HDS then HEN low or HEN then HDS low Data setup before HEN or HDS high HEN and HDS low for write HRW setup before HEN and HDS low HRW hold time after HEN or HDS high Data hold after HEN or HDS high HEN or HDS high to HEN and HDS low with HRW high for next read HEN or HDS high to HEN and HDS low for next write HRW rising to HREQ falling tmcdw tmdsu tmwpw tmrwsu tmrwhld tmdhw tmwtrd tmwd tmrwbsyl 0 8 24 24 8 8 30 30 12 ns ns ns ns ns ns ns ns ns tmcdr tmdd tmrpw tmdhr tmdis tmrd tmrdtw tmrwirqh 0 24 8 30 30 19 18 12 ns ns ns ns ns ns ns ns Symbol tmas tmah Min 5 5 Max Unit ns ns NOTES:1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the HREQ pin/bit should be observed to prevent overflowing the input data buffer. 24 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Host Management Interface (HMI) HADDR[3:0] t m as HDATA[7:0] HEN HRW HDS t m rwirqh HREQ t m dd t m rw su t m cdr t m rpw t m rd t m ah LSP t m dhr t m dis t m rdtw t m rw hld M SP Figure 14. Host Port Read Cycle Timing - Motorola Mode H A D D R [3 :0 ] t m as H D A T A [7 :0 ] HEN t m cdw HRW t m rw su HDS t m rw irq l HREQ t mwd t m w trd t m wpw t m r w h ld t m d su t m ah LSP t m dhw MSP Figure 15. Host Port Write Cycle Timing - Motorola Mode DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 25 CobraNet Hardware User's Manual Host Management Interface (HMI) 7.3 Host Port Timing - Intel(R) Mode (CL = 20 pF) Parameter Address setup before HCS and HRD low or HCS and HWR low Address hold time after HCS and HRD low or HCS and HWR high Read Delay between HRD then HCS low or HCS then HRD low Data valid after HCS and HRD low HCS and HRD low for read Data hold time after HCS or HRD high Data high-Z after HCS or HRD high HCS or HRD high to HCS and HRD low for next read HCS or HRD high to HCS and HWR low for next write HRD rising to HREQ rising Write Delay between HWR then HCS low or HCS then HWR low Data setup before HCS or HWR high HCS and HWR low for write Data hold after HCS or HWR high HCS or HWR high to HCS and HRD low for next read HCS or HWR high to HCS and HWR low for next write HWR rising to HREQ falling ticdw tidsu tiwpw tidhw tiwtrd tiwd tiwrbsyl 0 8 24 8 30 30 12 ns ns ns ns ns ns ns ticdr tidd tirpw tidhr tidis tird tirdtw tirdirqhl 0 24 8 30 30 18 18 12 ns ns ns ns ns ns ns ns Symbol tias tiah Min 5 5 Max Unit ns ns NOTES:1. The system designer should be aware that the actual maximum speed of the communication port may be limited by the firmware application. Hardware handshaking on the HREQ pin/bit should be observed to prevent overflowing the input data buffer. 26 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Host Management Interface (HMI) H A D D R [3 :0 ] t iah H D A T A [7 :0 ] HCS t icdr HW R HRD t ird irqh HREQ t irp w t ias t id d LSP t id hr t idis t ird t irdtw MSP Figure 16. Parallal Control Port - Intel Mode Read Cycle H A D D R [3:0] t iah H DATA[7:0] HCS t icdw HRD HW R t iwrbsyl HREQ t iw pw t idsu t iw d t iw trd t ias LSP t idhw MSP Figure 17. Parallel Control Port - Intel Mode Write Cycle DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 27 CobraNet Hardware User's Manual Host Management Interface (HMI) 7.4 Protocol and Messages The message conduit is used to issue commands to the CS1810xx/CS4961xx and retrieve HMI status. The data conduit is used to transfer data dependent on the HMI state as determined by commands issued by the host via the message conduit. 7.4.1 Messages Messages are used to efficiently invoke action in the CS1810xx/CS4961xx. To send a message, the host optionally writes to the A, B, and C registers. Writing to the D register transmits the message to the CS1810xx/CS4961xx. A listing of all HMI messages is shown in Table 4. Refer also to "HMI Definitions" on page 33 and "HMI Access Code" on page 34. Message Translate Address Acknowledge Interrupt Identify Goto Packet Transmit Buffer Goto Translation Acknowledge Packet Receipt Transmit Packet Goto Counters Goto Packet Receive Buffer Goto Translation DRQ Handshake Mode n/c n/c read write write n/c n/c read read read A Address (MS) n/c n/c n/c n/c n/c n/c n/c n/c n/c B Address n/c n/c n/c n/c n/c n/c n/c n/c n/c C Address (LS) n/c 7 6 5 4 3 2 1 0 0xB3 0xB4 0xB5 0xB5 0xB5 0xB5 0xB5 0xB5 0xB5 0xB5 D Table 4. HMI messages 28 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Host Management Interface (HMI) 7.4.1.1. Translate Address Translate Address does not actually update the address pointers but initiates the processing required to eventually move them. The host can accomplish other tasks, including HMI Reads and Writes while the address translation is being processed. A logical description of Translate Address is given below. A contextual use of the Translate Address operation is shown in the reference implementations. Refer also to "HMI Definitions" on page 33 and "HMI Access Code" on page 34. void TranslateAddress( long address ) { int msgack = MSG_D; MSG_A = ( address & 0xff0000 ) >> 16; MSG_B = ( address & 0xff00 ) >> 8; MSG_C = address & 0xff; MSG_D = CVR_TRANSLATE_ADDRESS; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); } 7.4.1.2. Interrupt Acknowledge Causes HACK to be de-asserted. void InterruptAck( void ) { int msgack = MSG_D; MSG_D = CVR_INTERRUPT_ACK; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); } 7.4.1.3. Goto Packet Moves HMI pointers to bridgeRxPktBuffer (write = 0) or bridgeTxPktBuffer (write = 1). void GotoPacket( bool write ) { int msgack = MSG_D; MSG_C = write ? MOP_GOTO_PACKET_TRANSMIT : MOP_GOTO_PACKET_RECEIVE; MSG_D = CVR_MULTIPLEX_OP; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); } 7.4.1.4. Goto Translation Moves HMI data pointers to the results of the most recently completed translate address operation. The write parameter dictates the operation of the HREQ signal and only needs to be supplied for applications using hardware data handshaking via this signal. void GotoTranslation( bool write = 0 ) { int msgack = MSG_D; MSG_C = write ? MOP_GOTO_TRANSLATION_WRITE : MOP_GOTO_TRANSLATION_READ; MSG_D = CVR_MULTIPLEX_OP; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); } DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 29 CobraNet Hardware User's Manual Host Management Interface (HMI) 7.4.1.5. Packet Received Sets bridgeRxPkt = bridgeRxReady thus acknowledging receipt of the packet in bridgeRxPktBuffer. void PacketReceive( void ) { int msgack = MSG_D; MSG_C = MOP_PACKET_RECEIVE; MSG_D = CVR_MULTIPLEX_OP; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); } 7.4.1.6. Packet Transmit Sets bridgeTxPkt = bridgeTxPktDone+1 thus initiating transmission of the contents of bridgeTxPktBuffer. Presumably bridgeTxPktBuffer has been previously written with valid packet data. void PacketTransmit( void ) { int msgack = MSG_D; MSG_C = MOP_PACKET_TRANSMIT; MSG_D = CVR_MULTIPLEX_OP; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); } 7.4.1.7. Goto Counters Moves HMI data pointers to interrupt status variables (beginning at hackStatus). void GotoCounters( void ) { int msgack = MSG_D; MSG_C = MOP_GOTO_COUNTERS; MSG_D = CVR_MULTIPLEX_OP; while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); } 30 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Host Management Interface (HMI) 7.4.2 Status HMI status can always be retrieved by reading the message conduit. Status is updated in a pipelined manner whenever the Message D register is read. Reading the message conduit gives the current status as of the last time the conduit was read. Bitfields in the HMI Status Register are outlined in Table 5 below. Refer also to "HMI Definitions" on page 33 and "HMI Access Code" on page 34. Status Reserved Region Length Reserved Writable Region Translation Complete Packet Transmission Complete Received Packet Available Message Togglebit Bit(s) [31:24] [23:8] [7:5] 4 3 2 1 0 Table 5. HMI status bits DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 31 CobraNet Hardware User's Manual Host Management Interface (HMI) 7.4.3 Data Before accessing data, address setup must be performed. Address setup consists of issuing a Translate Address request, waiting for the request to complete, then issuing a Goto Translation. Pipelining requires that a "garbage read" be performed following an address change. The second word read contains the data for the address requested. No similar pipelining issue exists with respect to write operations. 7.4.3.1. Region length Distance from the original pointer position (as per Translate Address) to the end of the instantiated region. A value of 0 indicates an invalid pointer. 7.4.3.2. Writable Region When set, this bit indicates the address pointer is positioned within a writable region. MI variables may be modified in a writable region by writing data to the data conduit. 7.4.3.3. Translation Complete When set, this bit indicates that the address translator is available (translation results are available and a new translation request may be submitted). This bit is cleared when a Translate Address message is issued and is set when the translation completes. 7.4.3.4. Packet Transmission Complete This bit is cleared when transmission is initiated by issuance of the Transmit Packet message. The bit is set when the packet has been transmitted and the transmit buffer is ready to accept a new packet. 7.4.3.5. Received Packet Available This bit is set when a packet is received into the packet bridge. It is cleared when the packet data is read and receipt is acknowledged by issuance of an Acknowledge Packet Receipt message. Note that Received Packet Available only goes low when there are no longer any pending received packets for the packet bridge. The packet bridge has the capacity to queue multiple packets in the receive direction. 7.4.3.6. Message Togglebit This bit toggles on completion of processing of each message. A safe means for the host to acknowledge processing of messages is as follows: void WaitToggle( void ) { int msgack = MSG_D; /* clean pipeline */ msgack = MSG_D; /* record current state of togglebit */ MSG_D = YOUR_COMMAND_HERE; /* issue command */ /* wait for togglebit to flip */ while( !( ( msgack ^ MSG_D ) & ( 1 << MSG_TOGGLE_BO ) ) ); } 32 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual HMI Reference Code 8.0 HMI Reference Code The following C code provides examples in using HMI messages, HMI status, and the HMI memory map. 8.1 HMI Definitions /*======================================================================== ** hmi.h ** CobraNet Host Management Interface example code ** Definitions **-----------------------------------------------------------------------** $Header$ ** Copyright (c) 2004, Peak Audio, a division of Cirrus Logic, Inc. **========================================================================*/ #define MSG_A 0 #define MSG_B 1 #define MSG_C 2 #define MSG_D 3 #define DATA_A 4 #define DATA_B 5 #define DATA_C 6 #define DATA_D 7 #define CONTROL 8 #define STATUS 9 #define CVR_SET_ADDRESS 0xb2 /* Not availbale on CS1810xx/CS4961xx/CM-2. */ /*CM-1 and Reference Design only. */ #define CVR_TRANSLATE_ADDRESS 0xb3 #define CVR_INTERRUPT_ACK 0xb4 #define CVR_MULTIPLEX_OP 0xb5 #define #define #define #define #define #define #define #define #define #define #define #define #define #define MOP_GOTO_TRANSLATION_READ 0 MOP_GOTO_TRANSLATION_WRITE 5 MOP_GOTO_PACKET_RECEIVE 1 MOP_GOTO_PACKET_TRANSMIT 6 MOP_GOTO_COUNTERS 2 MOP_PACKET_TRANSMIT 3 MOP_PACKET_RECEIPT 4 MOP_IDENTIFY 7 MSG_TOGGLE_BO 0 MSG_RXPACKET_BO 1 MSG_TXPACKET_BO 2 MSG_TRANSLATION_BO 3 MSG_WRITABLE_BO 4 MSG_LENGTH_BO 8 DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 33 CobraNet Hardware User's Manual HMI Reference Code 8.2 HMI Access Code /*======================================================================== ** hmi.c ** CobraNet Host Management Interface example code ** Simple edition **-----------------------------------------------------------------------** $Header$ ** Copyright (c) 2004, Peak Audio, a division of Cirrus Logic, Inc. **========================================================================*/ #include "hmi.h" /* variables model HMI state */ long PeekLimit; long PeekPointer = -1; long PokeLimit; long PokePointer = -1; /* access host port hardware */ #define HMI_BASE 0 unsigned char ReadRegister( int hmiregister ) { return *(unsigned char volatile *const) ( hmiregister + HMI_BASE ); } void WriteRegister( int hmiregister, unsigned char value ) { *(unsigned char volatile *const) ( hmiregister + HMI_BASE ) = value; } void SendMessage( unsigned char message ) { int msgack = ReadRegister( MSG_D ); /* issue (last byte of) message */ WriteRegister( MSG_D, message ); /* wait for acceptance of message */ while( !( ( msgack ^ ReadRegister( MSG_D ) ) & ( 1 << MSG_TOGGLE_BO ) ) ); } void SetAddress( long address ) { /* translate address */ WriteRegister( MSG_A, ( address & 0xff0000 ) >> 16 ); WriteRegister( MSG_B, ( address & 0xff00 ) >> 8 ); WriteRegister( MSG_C, address & 0xff ); SendMessage( CVR_TRANSLATE_ADDRESS ); /* wait for completion of translate address */ 34 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual HMI Reference Code while( !( ReadRegister( MSG_D ) & ( 1 << MSG_TRANSLATION_BO ) ) ); /* goto translation */ WriteRegister( MSG_C, MOP_GOTO_TRANSLATION_READ ); SendMessage( CVR_MULTIPLEX_OP ); /* "garbage" read clears data pipeline */ ReadRegister( DATA_D ); /* maintain local pointers */ PeekPointer = PokePointer = address; PeekLimit = PokeLimit = PeekPointer + ReadRegister( MSG_C ) + ( ReadRegister( MSG_B ) << 8 ); /* read-only region addressed */ if( !( ReadRegister( MSG_A ) & ( 1 << MSG_WRITABLE_BO ) ) ) { PokeLimit = PokePointer; } } unsigned long Peek( long address ) { if( address != PeekPointer ) { SetAddress( address ); } if( PeekPointer >= PeekLimit ) { throw "Peek addressing error!"; } unsigned long value = ReadRegister( DATA_A ) << 24; value += ReadRegister( DATA_B ) << 16; value += ReadRegister( DATA_C ) << 8; value += ReadRegister( DATA_D ); PeekPointer++; /* maintain local pointer */ return value; } void Poke( long address, unsigned long value ) { if( address != PokePointer ) { SetAddress( address ); } if( PokePointer >= PokeLimit ) { throw "Poke addressing error or read-only!"; } WriteRegister( DATA_A, (unsigned char) ( ( value >> 24 ) & 0xff ) ); WriteRegister( DATA_B, (unsigned char) ( ( value >> 16 ) & 0xff ) ); WriteRegister( DATA_C, (unsigned char) ( ( value >> 8 ) & 0xff ) ); WriteRegister( DATA_D, (unsigned char) ( value & 0xff ) ); /* maintain local pointers */ PokePointer++; PeekPointer = -1; /* force SetAddress()next Peek() to freshen data */ } DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 35 CobraNet Hardware User's Manual HMI Reference Code 8.3 CM-1, CM-2 Auto-detection The following function is useful for systems that support both the CM-1 and CM-2 or where a CobraNet interface is an optional add-in. Detect() returns 0 if no CobraNet interface module is detected, 1 for CM-1 and 2 for CM-2. int Detect( void ) { /* check for presence of CM-1 */ MSG_B = 0x55; /* write to CM-1 CVR register */ DATA_A = 0xaa; /* write to unused CM-1 register to flip data bus */ if( MSG_B == 0x55 ) { /* read back CVR */ /* redo same detection with different data */ MSG_B = 0x3c; DATA_A = 0xc3; if( MSG_B == 0x3c ) { return 1; /* CM-1 detected */ } } /* check for presence of CM-2 */ /* issue identify command */ MSG_C = MOP_IDENTIFY; MSG_D = CVR_MULTIPLEX_OP; int msgack = MSG_D; /* clean pipeline */ msgack = MSG_D; /* wait for togglebit to flip in response to command */ int tm0 = gettimeofday(); while( !( ( MSG_D ^ toggle ) & ( 1 << MSG_TOGGLE_BO ) ) ) { int tm1 = gettimeofday(); if( ( tm1 - tm0 ) > time_out ) { return 0; /* command timed out, no CobraNet interface present */ } } int garbage = MSG_D; /* clean pipeline */ /* verify identify results */ if( DATA_A == 'C' ) if( DATA_B == 'S' ) if( DATA_C == ( 18101 >> 8 ) ) if( DATA_D == ( 18101&0xff ) { return 2; /* CM-2 detected */ } return 0; /* no interface or non-supported interface */ } 36 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Mechanical Drawings and Schematics 9.0 Mechanical Drawings and Schematics The section contains detailed drawings of the CM-2 board and CS1810xx/CS4961xx device package design. The mechanical drawings are arranged as follows: * "CM-2 Module Assembly Drawing, Top" on page 38 * "General PCB Dimensions" on page 40 * "Example Configuration, Side View" on page 41 * "Faceplate Dimensions" on page 42 * "Connector Detail" on page 43 * "CM-2 RevF Schematic Page 1 of 7" on page 44 * "CM-2 RevF Schematic Page 2 of 7" on page 45 * "CM-2 RevF Schematic Page 3 of 7" on page 46 * "CM-2 RevF Schematic Page 4 of 7" on page 47 * "CM-2 RevF Schematic Page 5 of 7" on page 48 * "CM-2 RevF Schematic Page 6 of 7" on page 49 * "CM-2 RevF Schematic Page 7 of 7" on page 50 * "144-Pin LQFP Package Drawing" on page 51 DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 37 CobraNet Hardware User's Manual Mechanical Drawings and Schematics 9.1 CM-2 Mechanical Drawings Figure 18. CM-2 Module Assembly Drawing, Top 38 (c)Copyright 2005 Cirrus Logic, Inc. NOT TO SCALE DS651UM23 Version 2.3 CobraNet Hardware User's Manual Mechanical Drawings and Schematics Figure 19. CM-2 Module Assembly Drawing, Bottom DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. NOT TO SCALE 39 A20 B20 A1 A20 A1 0.3 2.86 3.500 NOT TO SCALE DS651UM23 Version 2.3 General PCB dimensions B1 (c)Copyright 2005 Cirrus Logic, Inc. Viewed from component side up. Component Side = J1 Bottom Side = J2 0.175 Figure 20. General PCB Dimensions Component Side = J3 Bottom Side = J4 B20 3.500 2x Mounting holes for front faceplate. B1 0.175 40 2x Mounting holes for PCB standoffs 4x 0.16 Hole, 0.3 pads CobraNet Hardware User's Manual Mechanical Drawings and Schematics CobraNet Hardware User's Manual Mechanical Drawings and Schematics 0.340 This distance accounts for the thickness of the faceplate Figure 21. Example Configuration, Side View DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. NOT TO SCALE 41 0.550 0.800 0.810 1.000 0.500 0.431 0.421 1.343 1.333 0.300 0.175 2x, Hole Diameter 0.160 1.000 max, 0.9 typ. Figure 22. Faceplate Dimensions Faceplate material is 20 guage, 0.037" thick Chrome plating on faceplate Faceplate Dimensions DS651UM23 Version 2.3 NOT TO SCALE 0.340 0.490 (c)Copyright 2005 Cirrus Logic, Inc. 0.300 0.862 42 Note: Mechanical dimensions for the CM-2 and CM-1 Rev F are identical. There are differences with earlier versions of the CM-1, however. For reference, earlier versions of the CM-1 dimensions are shown in RED. 3.500 4-40 PEM's, x2 0.175 CobraNet Hardware User's Manual Mechanical Drawings and Schematics 0.125 dia, 2x 0.680 0.700 CobraNet Hardware User's Manual Mechanical Drawings and Schematics Component Side Up J3 8x 0.047 Alignment holes J1 1.576 1.925 3.343 0.208 0.039 Connector Detail Figure 23. Connector Detail DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. NOT TO SCALE 43 0.157 CobraNet Hardware User's Manual Mechanical Drawings and Schematics 9.2 CM-2 Schematics connector connector.sch HRESET# HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# WATCHDOG MUTE# UART_TX_OE UART_TXD UART_RXD MCLK_OUT MCLK_IN REFCLK_IN FS1 SSI_CLK SSI_DIN[0..3] SSI_DOUT[0..3] RSVD[1..5] AUX_POWER[0..3] HRESET# HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# WATCHDOG MUTE# UART_TX_OE UART_TXD UART_RXD MCLK_OUT MCLK_IN REFCLK_IN FS1 SSI_CLK SSI_DIN[0..3] SSI_DOUT[0..3] RSVD[1..5] AUX_POWER[0..3] core core.sch HRESET# HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# WATCHDOG MUTE# UART_TX_OE UART_TXD UART_RXD MCLK_OUT MCLK_IN REFCLK_IN FS1 SSI_CLK SSI_DIN[0..3] SSI_DOUT[0..3] GPIO[0..1] RSVD[1..5] AUX_POWER[3..0] GPIO[0..1] is not used elsewhere. These pulldowns are used for test points and to keep these signals at valid levels. GPIO[0..1] GPIO0 GPIO1 R1 R2 10K Ohm GND This linear regulator is used to assure that the +1.8v rail quickly passes the 0.5v threshold at powerup, thus minimizing power sequencing issues and making sure that the DSP does not draw excessive power as the power rails ramp up. This linear regulator is set with Vout=1.22v, so it is effectively shut off once the switching regulator comes up. Further testing and characterization of the DSP is require to determine if this linear regulator is in fact required. U9 1 IN OUT BYP 2 GND LTC1761 ADJ 4 3 5 C45 0.01 uF U1 LTC3406-1.8 VCC_+3.3 4 1 C1 10 uF, X5R, 6.3 Volts VIN RUN GND SW Vout/FB 3 5 C2 2 C3 L1 2.2 uH VCC_+1.8 10 uF, X5R, 6.3 Volts This is a simple switching regulator. It produces 1.8V at >500 mA at about 90% efficency. A simple low drop out linear regulator would be a cheaper alternative at the expense of power. A linear regulator would dissapate about 0.75 watts max, This switching regulator dissapates about 0.10 watts max. Figure 24. CM-2 RevF Schematic Page 1 of 7 44 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 HRESET# 6 GND 74LVC32 5 DATA[0..15] ADDR[0..19] 16 LED_CTRL[0..2] VCC_+3.3 LED_CTRL0 LED_CTRL1 LED_CTRL2 GND VCC GND 8 R12 3.3K Ohm A1 B1 C1 D1 CTRL CTRL CTRL CTRL GND OUT OUT VCXO_OUT VCXO_OUT AB3 CD3 MCLK_IN MCLK_SEL MCLK_IN VCXO_OUT VCC VCC VCC A4 B4 CD4 16 C19 0.1 uF AB2 C2 D2 GND GND GND 24.576 MHz VCXO VCC_+3.3 VCC GND GND G A/B 1A 2A 3A 4A 1B 2B 3B 4B GND GND GND C21 0.1 uF 8 DS651UM23 Version 2.3 HRESET# 4 U10B macphy1 macphy1.sch HRESET_BUF# CLK_25 CLK_25 HRESET_BUF# HRESET_BUF# HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# MAC_CS# OE# WE# IOWAIT ADDR[0..19] DATA[0..15] AUX_POWER[0..3] AUX_POWER[3..0] AUX_POWER[3..0] MAC_IRQ0 MAC_IRQ0 MAC_IRQ0 LED_CTRL[0..2] LED_BUF[0..7] LED_CTRL[0..2] LED_BUF[0..7] MAC_CS# OE# WE# IOWAIT ADDR[0..19] DATA[0..15] MAC_CS# OE# WE# IOWAIT ADDR[0..19] DATA[0..15] UART_TX_OE UART_TXD UART_RXD macphy2 macphy2.sch HRESET_BUF# CLK_25 CLK_25 FS1 SSI_CLK SSI_DIN[0..3] SSI_DOUT[0..3] GPIO[0..1] AUX_POWER[0..3] REFCLK_IN WATCHDOG MUTE# MAC_IRQ1 RSVD[1..5] VCC_+3.3 VCC_+3.3 MAC_IRQ1 MAC_IRQ1 LED_BUF[0..7] LED_BUF[0..7] MAC_CS# OE# WE# IOWAIT ADDR[0..19] DATA[0..15] VCXO_CTRL MCLK_SEL MCLK_INTERNAL flash flash.sch HRESET_BUF# CLK_25 FLASH_CS# FLASH_CS# R4 30.9 Ohm, 1% C15 0.1 uF R5 30.9 Ohm, 1% U2 R6 30.9 Ohm, 1% R7 10 11 14 12 13 SCLR# SCK DIN RCK OE# 30.9 Ohm, 1% R8 30.9 Ohm, 1% CASCADE 9 74LV595 R9 30.9 Ohm, 1% R10 30.9 Ohm, 1% R11 30.9 Ohm, 1% C20 0.1 uF LED_BUF6 LED_BUF7 C18 0.1 uF LED_BUF4 LED_BUF5 Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7 C17 0.1 uF LED_BUF2 C16 0.1 uF LED_BUF0 LED_BUF1 FLASH_CS# OE# WE# ADDR[0..19] DATA[0..15] dsp dsp.sch HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# HEN# HRW HDS# HADDR[0..3] HDATA[0..7] HREQ# HACK# UART_TX_OE UART_TXD UART_RXD UART_TX_OE UART_TXD UART_RXD FS1 SSI_CLK SSI_DIN[0..3] SSI_DOUT[0..3] FS1 SSI_CLK SSI_DIN[0..3] SSI_DOUT[0..3] GPIO[0..1] GPIO[0..1] REFCLK_IN WATCHDOG MUTE# REFCLK_IN WATCHDOG MUTE# RSVD[1..5] RSVD[1..5] VCXO_CTRL MCLK_SEL MCLK_INTERNAL CLK_25 LED_BUF[0..7] 15 1 2 3 4 5 6 7 LED_BUF3 Figure 25. CM-2 RevF Schematic Page 2 of 7 VCC_+3.3 VCC_+3.3 U3 1Y 2Y 3Y 4Y 4 7 9 12 R44 24.9 Ohm, 1% MCLK_INTERNAL R16 24.9 Ohm, 1% MCLK_OUT MCLK_OUT 15 1 2 5 11 14 3 6 10 13 U4 74LVC157 VCC_+3.3 C22 0.1 uF (c)Copyright 2005 Cirrus Logic, Inc. LED Filters go close to the connector. RN2 VCXO_CTRL MCLK_SEL WATCHDOG 1 VCC_+3.3 VCXO_CTRL 2 3 4 5 7 8 9 10 6 10K Ohm, 8x Array VCC_+3.3 MUTE# IOWAIT R3 10K Ohm R15 3.3K Ohm GND GND CobraNet Hardware User's Manual Mechanical Drawings and Schematics 45 ADDR[0..19] ADDR[0..19] U5 37 VCC GND GND 27 VCC_+3.3 C23 0.1 uF 46 46 VCC_+3.3 ADDR0 DATA[0..15] DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 GND VCC_+3.3 VCC_+3.3 ADDR19 ADDR18 ADDR17 ADDR16 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 HRESET_BUF# 10 NC HRESET_BUF# 12 RESET# CE# WE# OE# BYTE# NC/VPP NC/WP# NC/RY/BY# 47 13 14 15 26 11 28 FLASH_TSOP FLASH_CS# WE# OE# 9 16 17 48 1 2 3 4 5 6 7 8 18 19 20 21 22 23 24 25 NC/A19 NC/A18 A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D15/A-1 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 45 43 41 39 36 34 32 30 44 42 40 38 35 33 31 29 DATA[0..15] FLASH_CS# WE# OE# CobraNet Hardware User's Manual Mechanical Drawings and Schematics Figure 26. CM-2 RevF Schematic Page 3 of 7 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 GND 8 10 VCC_+1.8 74LVC32 9 U10C D1 1N4148W VCC_+1.8 VCC_+1.8 8 2 6 4 8 2 6 4 8 2 6 4 3.3K Ohm C52 0.1 uF R56 VCC_+3.3 R13 R14 VCC 1 7 3 5 1 7 3 5 1 7 3 5 8 2 6 4 8 2 6 4 8 2 6 4 DEBUG_DATA CON4 GND R57 10K Ohm GND GND GND G A/B 1A 2A 3A 4A 1B 2B 3B 4B 1Y 2Y 3Y 9 12 7 4 R53 FS1 Debug Port 5 1 7 3 5 VCC_+3.3 C53 0.1 uF 1 7 3 5 1 7 3 VCC_+1.8 VCC_+3.3 GND 10 24 54 66 83 98 119 130 18 33 44 60 91 113 136 73 4 3 9 U6 VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDD VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO VDDIO HRESET_BUF# OE# WE# FLASH_CS# MAC_CS# HADDR3 HADDR2 HADDR1 HADDR0 HDATA7 HDATA6 HDATA5 HDATA4 HDATA3 HDATA2 HDATA1 HDATA0 DAO_MCLK 8 MCLK_INTERNAL 111 112 114 115 117 118 120 121 HDATA7 HDATA6 HDATA5 HDATA4 HDATA3 HDATA2 HDATA1 HDATA0 HDATA[0..7] MCLK_INTERNAL R54 24.9 Ohm, 1% SSI_DOUT[0..3] DAO2_LRCLK RSVD5 RSVD4 RSVD2 RSVD1 RSVD[1..5] DAI1_LRCLK DAI1_SCLK DAI1_DATA3 DAI1_DATA2 DAI1_DATA1 DAI1_DATA0 NC NC 138 137 131 132 134 135 141 142 DAO1_LRCLK SSI_CLK_J SSI_DIN3 SSI_DIN2 SSI_DIN1 SSI_DIN0 SSI_DIN[0..3] RSVD3 RSVD[1..5] 14 12 5 6 7 11 DAO2_LRCLK NC NC NC NC HS3 105 106 109 110 HADDR3 HADDR2 HADDR1 HADDR0 HADDR[0..3] OE# WE# FLASH_CS# MAC_CS# IOWAIT EXT_OE# EXT_WE# EXT_CS1# EXT_CS2# IOWAIT 89 38 90 65 96 RESET# DBCK DBDA HRESET_BUF# 93 HR/W# HDS# HEN# HACK# HREQ# HRW HDS# HEN# HACK# HREQ# 107 103 104 102 140 TEST HRW HDS# HEN# HACK# HREQ# IOWAIT HADDR[0..3] HDATA[0..7] DATA15 DATA14 DATA13 DATA12 DATA11 DATA10 DATA9 DATA8 DATA7 DATA6 DATA5 DATA4 DATA3 DATA2 DATA1 DATA0 40 41 42 43 45 46 48 49 29 30 31 32 34 35 37 39 SD_D15/EXT_D7 SD_D14/EXT_D6 SD_D13/EXT_D5 SD_D12/EXT_D4 SD_D11/EXT_D3 SD_D10/EXT_D2 SD_D9/EXT_D1 SD_D8/EXT_D0 SD_D7/EXT_D15 SD_D6/EXT_D14 SD_D5/EXT_D13 SD_D4/EXT_D12 SD_D3/EXT_D11 SD_D2/EXT_D10 SD_D1/EXT_D9 SD_D0/EXT_D8 DAO1_LRCLK DAO1_SCLK DAO1_DATA3 DAO1_DATA2/HS2 DAO1_DATA1/HS1 DAO1_DATA0/HS0 22 20 15 16 17 19 DAO1_LRCLK SSI_CLK_J SSI_DOUT3 SSI_DOUT2 SSI_DOUT1 SSI_DOUT0 DATA[0..15] SSI_CLK 8 CN12 0.1 uF, 4x Array VCC_+3.3 CN3 0.1 uF, 4x Array CN5 0.1 uF, 4x Array 1 2 3 4 U11 74LVC157 GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC NC NC NC NC NC GND_A VDD_A 13 21 27 36 47 57 63 69 76 86 94 101 116 122 133 139 28 50 51 52 53 78 79 80 81 126 129 C42 2.2 uF, X7R, 1206 C43 1000 pF, COG R42 R46 R48 R50 R43 R47 R49 R51 DS651UM23 Version 2.3 CN2 0.1 uF, 4x Array VCC_+3.3 GND DAO1_LRCLK GND GND GND 4Y CN4 0.1 uF, 4x Array CN1 0.1 uF, 4x Array 16 FS1 3.3K Ohm DAO2_LRCLK VCC_+3.3 DEBUG_CLK JP1 VCC_+3.3 VCC_+3.3 15 1 2 5 11 14 3 6 10 13 SSI_CLK DATA[0..15] SSI_DOUT[0..3] RSVD[1..5] ADDR19 ADDR18 ADDR17 ADDR16 ADDR15 ADDR14 ADDR13 ADDR12 ADDR11 ADDR10 ADDR9 ADDR8 ADDR7 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 88 87 85 84 82 75 77 55 56 74 58 59 61 62 64 67 68 70 71 72 EXT_A19 EXT_A18 EXT_A17 EXT_A16 EXT_A15 SD_A14/EXT_A13 SD_A13/EXT_A14 SD_A12/EXT_A11 SD_A11/EXT_A10 SD_A10/EXT_A12 SD_A9/EXT_A9 SD_A8/EXT_A8 SD_A7/EXT_A7 SD_A6/EXT_A6 SD_A5/EXT_A5 SD_A4/EXT_A4 SD_A3/EXT_A3 SD_A2/EXT_A2 SD_A1/EXT_A1 SD_A0/EXT_A0 UART_TX_OE UART_TXD UART_RXD XTAL_OUT XTO XTI FILT2 FILT1 23 25 26 ADDR[0..19] UART_TX_OE UART_TXD UART_RXD 24.9 Ohm, 1% R45 123 124 125 127 128 2 25 MHz UART_TX_OE UART_TXD UART_RXD SSI_DIN[0..3] Figure 27. CM-2 RevF Schematic Page 4 of 7 GPIO2 GPIO1 GPIO0 REFCLK_IN WATCHDOG_OUT MUTE# MCLK_SEL IRQ1 IRQ2 VCXO_CTRL 108 100 99 97 95 92 2 143 144 1 GPIO1 GPIO0 REFCLK_IN WATCHDOG MUTE# MCLK_SEL MAC_IRQ1 MAC_IRQ0 VCXO_CTRL REFCLK_IN WATCHDOG MUTE# MCLK_SEL MAC_IRQ1 MAC_IRQ0 VCXO_CTRL Y1 1 CS18101 FB1 VCC_DSPA R55 1 MegOhm C41 22 pF R41 5.90K Ohm C4 FBEAD, 68 Ohm @ 100 MHz C24 0.1 uF 10 uF, X5R, 6.3 Volts C5 VCC_+1.8 C44 0.1 uF 10 uF, X5R, 6.3 Volts (c)Copyright 2005 Cirrus Logic, Inc. ADDR[0..19] GPIO[0..1] GPIO[0..1] CLK_25 CLK_25 C40 22 pF VCC_+3.3 3.3K Ohm Default Boot Mode: HS3 - Down HS2 - Down HS1 - Up HS0 - Down RSVD1 SSI_DOUT2 SSI_DOUT1 SSI_DOUT0 These pullups and pulldowns are used to set the boot mode of the DSP. The appropriate resistor is installed to select the boot mode. 3.3K Ohm CobraNet Hardware User's Manual Mechanical Drawings and Schematics 47 8 2 6 4 8 2 6 4 8 2 6 CN6 0.1 uF, 4x Array CN7 0.1 uF, 4x Array 4 CN8 0.1 uF, 4x Array 5 1 7 3 5 1 7 3 5 1 7 LED_CTRL[0..2] LED_CTRL[0..2] 3 LED_BUF2 LED_BUF3 LED_BUF0 5 20 36 55 72 73 90 27 28 35 48 19 18 17 16 62 61 60 71 70 69 68 0.1 uF U7 C27 R20 49.9 Ohm, 1% GND 0.1 uF 9 TXDTXO+ TXO10 RXI+ RXIC28 GND 0.1 uF 12 RXDH2006A R18 R17 49.9 Ohm, 1% 11 29 30 33 34 RXD+ 8 7 TXD+ TXD+ 18 17 16 TXDRXD+ 15 14 13 RXDJ5 RJ45 L4 L3 L2 DVDD DVDD DVDD DVDD DVDD DVDD DVDD AVDD AVDD AVDD TEST5 TEST4 TEST3 TEST2 TEST1 MAC_IRQ0 MAC_IRQ0 100 79 INT WAKEUP LINKACT# DUP# SPEED# HRESET_BUF# HRESET_BUF# 14 80 RST PW_RST# GPIO3 GPIO2 GPIO1 GPIO0 L1 LED_BUF1 74LVC32 VCC_+3.3 VCC_PHY1 GND T1B VCC_PHY1 GND VCC_PHY1 LED_CTRL2 LED_CTRL1 LED_CTRL0 R27 R28 TX_CLK TXD0 TXD1 TXD2 TXD3 TX_EN 49 50 51 52 53 54 C25 0.1 uF 75 Ohm, 1% R29 R30 R31 R32 DGND DGND DGND DGND DGND DGND DGND DGND AGND AGND NC NC NC X2_25M X1_25M CLK20MO BGRES BGGND 15 23 42 58 63 76 81 99 31 32 74 75 77 21 22 59 26 25 CLK_25 14 74LVC32 GND VCC 7 Figure 28. CM-2 RevF Schematic Page 5 of 7 VCC_+3.3 C26 WE# MAC_CS# IOWAIT ADDR0 ADDR2 ADDR3 ADDR1 ADDR4 VCC_+3.3 VCC_+3.3 SA4 SA5 SA6 SA7 SA8 SA9 1 2 3 4 91 92 IOR# IOW# AEN IOWAIT IO16 CMD 93 94 95 96 97 98 RX_CLK RXD0 RXD1 RXD2 RXD3 RX_DV RX_ER 47 38 39 40 41 45 46 CRS COL LINK_O LINK_I SD MDC MDIO EEDI EEDO EECK EECS 57 56 43 44 78 37 24 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 6 7 8 9 10 11 12 13 89 88 87 86 85 84 83 82 DM9000 64 65 66 67 R25 6.8K Ohm, 1% RN7 1 GND CLK_25 48 FB2 VCC_+3.3 FBEAD, 68 Ohm @ 100 MHz C6 C46 0.01 uF 10 uF, X5R, 6.3 Volts C7 VCC_PHY1 10 uF, X5R, 6.3 Volts VCC_+3.3 VCC_+3.3 VCC_PHY1 LED_BUF[0..7] R19 49.9 Ohm, 1% LED_BUF[0..7] 3 S1 S2 SHIELD SHIELD 1 2 3 4 5 6 7 8 FB3 AUX_POWER0 FB4 AUX_POWER1 FB5 AUX_POWER2 FB6 AUX_POWER3 FBEAD, 68 Ohm @ 100 MHz 75 Ohm, 1% OE# OE# 1 U10A CobraNet Hardware User's Manual Mechanical Drawings and Schematics MAC_CS# MAC_CS# 2 WE# IOWAIT ADDR[0..19] ADDR[0..19] Note: See Text Warning C48 0.01 uF, 2KV SHIELD AUX_POWER[0..3] AUX_POWER[0..3] (c)Copyright 2005 Cirrus Logic, Inc. Keep res close to chip pins. 2 3 4 5 7 8 9 10 6 3.3K Ohm, 8x Array GND VCC_+3.3 VCC_+3.3 U10E C51 0.1 uF DATA[0..15] DATA[0..15] Warning: Failure to properly install and configure the aux. Ethernet signals can result in very bad things (i.e., fire, smoke, bad hair days). If power is supplied via the RJ-45 connector then only the ferrite beads are installed (not the resistors). If power is not supplied via the RJ-45 then the resistors are installed and the beads are not. DS651UM23 Version 2.3 i h FB7 VCC_+3.3 FBEAD, 68 Ohm @ 100 MHz C8 C47 0.01 uF 10 uF, X5R, 6.3 Volts C9 VCC_PHY2 8 2 6 4 8 2 6 4 8 2 6 CN9 0.1 uF, 4x Array CN10 0.1 uF, 4x Array 4 CN11 0.1 uF, 4x Array 5 1 7 3 5 1 7 3 5 1 7 3 LED_BUF6 TXD+ 21 20 19 LED_BUF7 LED_BUF4 L4 L3 L2 TXDRXD+ 24 5 20 36 55 72 73 90 27 28 35 48 19 18 17 16 62 61 60 71 70 69 68 U8 C31 0.1 uF 6 TXDTXO+ TXO33 34 1 RXI+ RXIGND 0.1 uF 3 RXDR21 H2006A 29 30 C32 2 RXD+ DVDD DVDD DVDD DVDD DVDD DVDD DVDD AVDD AVDD AVDD TEST5 TEST4 TEST3 TEST2 TEST1 GPIO3 GPIO2 GPIO1 GPIO0 GND 5 R24 49.9 Ohm, 1% MAC_IRQ1 MAC_IRQ1 100 79 INT WAKEUP LINKACT# DUP# SPEED# HRESET_BUF# HRESET_BUF# 14 80 RST PW_RST# L1 LED_BUF5 R22 49.9 Ohm, 1% R33 R34 R52 3.3K Ohm VCC_+3.3 C29 0.1 uF 75 Ohm, 1% R35 R36 R37 R38 DGND DGND DGND DGND DGND DGND DGND DGND AGND AGND NC NC NC X2_25M X1_25M CLK20MO BGRES BGGND EEDI EEDO EECK EECS 15 23 42 58 63 76 81 99 31 32 74 75 77 21 22 59 26 25 64 65 66 67 CLK_25 DS651UM23 Version 2.3 10 uF, X5R, 6.3 Volts VCC_+3.3 VCC_+3.3 VCC_PHY2 LED_BUF[0..7] R23 49.9 Ohm, 1% 11 VCC_+3.3 VCC_+3.3 VCC_PHY2 0.1 uF 4 TXD+ GND VCC_PHY2 GND T1A C30 VCC_PHY2 LED_BUF[0..7] S1 S2 23 22 RXDJ6 RJ45 SHIELD SHIELD WE# MAC_CS# IOWAIT ADDR0 ADDR2 ADDR3 ADDR1 ADDR4 VCC_+3.3 VCC_+3.3 93 94 95 96 97 98 SA4 SA5 SA6 SA7 SA8 SA9 1 2 3 4 5 6 7 8 1 2 3 4 91 92 IOR# IOW# AEN IOWAIT IO16 CMD RX_CLK RXD0 RXD1 RXD2 RXD3 RX_DV RX_ER 47 38 39 40 41 45 46 FB8 AUX_POWER0 AUX_POWER1 FB9 AUX_POWER2 FB10 AUX_POWER3 FB11 FBEAD, 68 Ohm @ 100 MHz TX_CLK TXD0 TXD1 TXD2 TXD3 TX_EN 49 50 51 52 53 54 75 Ohm, 1% MAC_CS# MAC_CS# 12 U10D OE# OE# 13 74LVC32 WE# IOWAIT ADDR[0..19] ADDR[0..19] Note: See Text Warning C49 0.01 uF, 2KV SHIELD AUX_POWER[0..3] AUX_POWER[0..3] Figure 29. CM-2 RevF Schematic Page 6 of 7 CRS COL LINK_O LINK_I SD MDC MDIO 57 56 DATA0 DATA1 DATA2 DATA3 DATA4 DATA5 DATA6 DATA7 DATA8 DATA9 DATA10 DATA11 DATA12 DATA13 DATA14 DATA15 6 7 8 9 10 11 12 13 89 88 87 86 85 84 83 82 SD0 SD1 SD2 SD3 SD4 SD5 SD6 SD7 SD8 SD9 SD10 SD11 SD12 SD13 SD14 SD15 43 44 78 37 24 DM9000 R26 6.8K Ohm, 1% RN8 1 GND CLK_25 (c)Copyright 2005 Cirrus Logic, Inc. Keep res close to chip pins. 2 3 4 5 7 8 9 10 6 3.3K Ohm, 8x Array GND DATA[0..15] DATA[0..15] Warning: Failure to properly install and configure the aux. Ethernet signals can result in very bad things (i.e., fire, smoke, bad hair days). If power is supplied via the RJ-45 connector then only the ferrite beads are installed (not the resistors). If power is not supplied via the RJ-45 then the resistors are installed and the beads are not. The secondary Ethernet MAC and connector are optional. If it is not required then all parts on this page can be depopulated (or removed entirely from a new design based on this circuit). CobraNet Hardware User's Manual Mechanical Drawings and Schematics 49 1 1 1 R39 0 Ohm 1 50 J1 UART_TXD UART_TXD RN3 1 GND 2 3 4 5 7 8 9 10 J2 Note: Pull-ups/downs on SSI_DOUT[0..4] are located on the DSP schematic page. SSI_DIN3 SSI_DIN2 SSI_DIN1 SSI_DIN0 RSVD5 SSI_DOUT3 RSVD3 RSVD4 6 10K Ohm, 8x Array GND RN4 1 GND RSVD1 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 RSVD1 GND VCC_+3.3 GND VCC_+3.3 CNM_CONN40 2 3 4 5 7 8 9 10 SSI_CLK MCLK_IN FS1 RSVD2 HADDR3 HDATA7 HDATA6 HDATA5 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 UART_RXD UART_TX_OE HACK# HRW HDS# HREQ# HEN# HADDR0 HADDR1 HADDR2 HDATA0 HDATA1 HDATA2 HDATA3 HDATA4 HDATA5 HDATA6 HRESET# HDATA7 HADDR3 UART_RXD UART_TX_OE HACK# HRW HDS# HREQ# HEN# HADDR0 HADDR1 HADDR2 HDATA0 HDATA1 HDATA2 HDATA3 HDATA4 HDATA5 HDATA6 HRESET# HDATA7 HADDR3 CNM_CONN40 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 6 10K Ohm, 8x Array GND J3 J4 2 3 4 5 7 8 9 10 HDATA3 HDATA2 HDATA1 HDATA0 HADDR0 HADDR1 HADDR2 HDATA4 RN5 1 GND 6 10K Ohm, 8x Array GND RN6 1 VCC_+3.3 RSVD2 MUTE# FS1 MCLK_OUT MCLK_IN REFCLK_IN SSI_CLK SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3 SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3 RSVD3 WATCHDOG RSVD4 AUX_POWER2 AUX_POWER0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND GND VCC_+5 VCC_+5 AUX_POWER3 AUX_POWER1 CNM_CONN40 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND VCC_+3.3 GND GND VCC_+5 VCC_+5 AUX_POWER3 AUX_POWER1 CNM_CONN40 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 RSVD2 MUTE# FS1 MCLK_OUT MCLK_IN REFCLK_IN SSI_CLK SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3 SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3 RSVD3 WATCHDOG RSVD4 AUX_POWER2 AUX_POWER0 HEN# HREQ# HDS# HACK# UART_TXD UART_RXD UART_TX_OE REFCLK_IN 2 3 4 5 7 8 9 10 6 10K Ohm, 8x Array VCC_+3.3 These pullups/downs are used to assure a valid logic level if a signal is tri-stated or not connected. In some situations, these may not be required. M3 MOUNTING These two mounting holes are located near the front panel of the CM-2. VCC_+3.3 C33 0.1 uF C34 0.1 uF C35 0.1 uF C36 0.1 uF C37 0.1 uF C38 0.1 uF VCC_+5 C39 0.1 uF HRESET# HACK# HRW HDS# HREQ# HEN# HRESET# HACK# HRW HDS# HREQ# HEN# HDATA[0..7] HDATA[0..7] HDATA0 HDATA1 HDATA2 HDATA3 HDATA4 HDATA5 HDATA6 HDATA7 HADDR[0..3] HADDR[0..3] HADDR0 HADDR1 HADDR2 HADDR3 SSI_DOUT[0..3] SSI_DOUT[0..3] SSI_DOUT0 SSI_DOUT1 SSI_DOUT2 SSI_DOUT3 CobraNet Hardware User's Manual Mechanical Drawings and Schematics SSI_DIN[0..3] SSI_DIN[0..3] SSI_DIN0 SSI_DIN1 SSI_DIN2 SSI_DIN3 SSI_CLK MCLK_IN MCLK_OUT FS1 REFCLK_IN UART_TX_OE UART_TXD UART_RXD SSI_CLK MCLK_IN MCLK_OUT FS1 REFCLK_IN UART_TX_OE UART_TXD UART_RXD AUX_POWER[0..3] AUX_POWER[0..3] AUX_POWER0 AUX_POWER1 AUX_POWER2 AUX_POWER3 WATCHDOG MUTE# WATCHDOG MUTE# RSVD[1..5] RSVD[1..5] RSVD1 RSVD2 RSVD3 RSVD4 RSVD5 Figure 30. CM-2 RevF Schematic Page 7 of 7 AC Signal Return Path Caps M4 MOUNTING These two mounting holes are located at the "back" of the CM-2, near the main interface connectors. R40 0 Ohm VCC_+3.3 C10 C11 C12 C13 10 uF, X5R, 6.3 Volts 10 uF, X5R, 6.3 Volts 10 uF, X5R, 6.3 Volts 10 uF, X5R, 6.3 Volts (c)Copyright 2005 Cirrus Logic, Inc. Power Decoupling Caps SHIELD M1 MOUNTING M2 MOUNTING Note: Similar AC signal return path caps must be included on the motherboard near the connector. C14 10 uF, X5R, 6.3 Volts C50 Place near the Ethernet connectors. DS651UM23 Version 2.3 0.01 uF, 2KV CobraNet Hardware User's Manual Mechanical Drawings and Schematics 9.3 CS1810xx/CS4961xx Package E E1 D D1 Notes: 1. Controlling dimension is millimeter. 2. Dimensioning and tolerancing per ASME Y14.5M-1994. e b SEATING PLANE ddd M B B L1 A A1 L Figure 31. 144-Pin LQFP Package Drawing MILLIMETERS INCHES MAX 1.60 0.15 0.27 MIN --.002" .007" NOM ----.009" .866" .787" .866" .787" .020" 7 0.75 0 .018" --.024" .039" REF .003" 7 .030" MAX .063" .006" .011" DIM MIN A A1 b D D1 E E1 e --0.05 0.17 NOM ----0.22 22.00 BSC 20.00 BSC 22.00 BSC 20.00 BSC 0.50 BSC 0 0.45 --0.60 1.00 REF TOLERANCES OF FORM AND POSITION ddd 0.08 L L1 DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 51 CobraNet Hardware User's Manual Mechanical Drawings and Schematics 9.4 Temperature Specifications * Thermal Coefficient (junction-to-ambient): ja - 38 C / Watt * Ambient Temperature Range: 0-70 deg C * Junction Temperature Range: 0-125 deg C 52 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 CobraNet Hardware User's Manual Ordering Information 10.0 Ordering Information 10.1 Device Part Numbers CS181002-CQ/A1 CS181012-CQ/A1 CS181022-CQ/A1 CS181002-CQZ/A1 CS181012-CQZ/A1 CS181022-CQZ/A1 CS496102-CQZ/A1 CS496112-CQZ/A1 CS496122-CQZ/A1 2x2 Channels 8x8 Channels 16x16 Channels 2x2 Channels 8x8 Channels 16x16 Channels 2x2 Channels + DSP 8x8 Channels + DSP 16x16 Channels + DSP 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 0C to +70C 144-pin LQFP 144-pin LQFP 144-pin LQFP 144-pin LQFP 144-pin LQFP 144-pin LQFP 144-pin LQFP 144-pin LQFP 144-pin LQFP Lead Free Lead Free Lead Free Lead Free Lead Free Lead Free 10.2 Device Part Numbering Scheme CS1810x 2 -- CQZ/A1 Die Revision Base Part Number Channel Count Designator: 0 = 2x2 1 = 8x8 2 = 16x16 ROM Version (ROM ID) Lead-free Designator: Z = Lead-free Device Packaging (not present if device contains lead) Package Type: Q = LQFP (144-pin) Temperature Grade Designator: C = Commercial (0C to +70C) CS4961x 2 -- CQZ/A1 Die Revision Base Part Number Channel Count Designator: 0 = 2x2 1 = 8x8 2 = 16x16 ROM Version (ROM ID) Note: Lead-free Designator: Z = Lead-free Device Packaging (not present if device contains lead) Package Type: Q = LQFP (144-pin) Temperature Grade Designator: C = Commercial (0C to +70C) Go to the Cirrus Logic Internet site at http://www.cirrus.com to find contact information for your local sales representative. Figure 32. Device Part Numbering Explanation DS651UM23 Version 2.3 (c)Copyright 2005 Cirrus Logic, Inc. 53 CobraNet Hardware User's Manual Ordering Information Contacting Cirrus Logic Support For all product questions and inquiries contact a Cirrus Logic Sales Representative. To find the one nearest to you go to www.cirrus.com IMPORTANT NOTICE Cirrus Logic, Inc. and its subsidiaries ("Cirrus") believe that the information contained in this document is accurate and reliable. However, the information is subject to change without notice and is provided "AS IS" without warranty of any kind (express or implied). Customers are advised to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgment, including those pertaining to warranty, indemnification, and limitation of liability. No responsibility is assumed by Cirrus for the use of this information, including use of this information as the basis for manufacture or sale of any items, or for infringement of patents or other rights of third parties. This document is the property of Cirrus and by furnishing this information, Cirrus grants no license, express or implied under any patents, mask work rights, copyrights, trademarks, trade secrets or other intellectual property rights. Cirrus owns the copyrights associated with the information contained herein and gives consent for copies to be made of the information only for use within your organization with respect to Cirrus integrated circuits or other products of Cirrus. This consent does not extend to other copying such as copying for general distribution, advertising or promotional purposes, or for creating any work for resale. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS MAY INVOLVE POTENTIAL RISKS OF DEATH, PERSONAL INJURY, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). CIRRUS PRODUCTS ARE NOT DESIGNED, AUTHORIZED OR WARRANTED FOR USE IN AIRCRAFT SYSTEMS, MILITARY APPLICATIONS, PRODUCTS SURGICALLY IMPLANTED INTO THE BODY, AUTOMOTIVE SAFETY OR SECURITY DEVICES, LIFE SUPPORT PRODUCTS OR OTHER CRITICAL APPLICATIONS. INCLUSION OF CIRRUS PRODUCTS IN SUCH APPLICATIONS IS UNDERSTOOD TO BE FULLY AT THE CUSTOMER'S RISK AND CIRRUS DISCLAIMS AND MAKES NO WARRANTY, EXPRESS, STATUTORY OR IMPLIED, INCLUDING THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR PARTICULAR PURPOSE, WITH REGARD TO ANY CIRRUS PRODUCT THAT IS USED IN SUCH A MANNER. IF THE CUSTOMER OR CUSTOMER'S CUSTOMER USES OR PERMITS THE USE OF CIRRUS PRODUCTS IN CRITICAL APPLICATIONS, CUSTOMER AGREES, BY SUCH USE, TO FULLY INDEMNIFY CIRRUS, ITS OFFICERS, DIRECTORS, EMPLOYEES, DISTRIBUTORS AND OTHER AGENTS FROM ANY AND ALL LIABILITY, INCLUDING ATTORNEYS' FEES AND COSTS, THAT MAY RESULT FROM OR ARISE IN CONNECTION WITH THESE USES. Cirrus Logic, Cirrus, and the Cirrus Logic logo designs are trademarks of Cirrus Logic, Inc. All other brand and product names in this document may be trademarks or service marks of their respective owners. Motorola is a registered trademark of Motorola, Inc. Intel is a registered trademark of Intel, Inc. 54 (c)Copyright 2005 Cirrus Logic, Inc. DS651UM23 Version 2.3 |
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